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Beilstein J. Nanotechnol. 2018, 9, 1844–1855, doi:10.3762/bjnano.9.176
Figure 1: Basic designs of (a) M-PLL and (b) S-PLL circuits.
Figure 2: Basic concepts of different PC designs using (a) a LPF, (b) a BPF, (c) a BEF and (d) a HPF. (i) Pri...
Figure 3: Block diagrams of the implemented (a) M-PLL and (b) S-PLL.
Figure 4: Performance of the implemented PD–PC units with (a) a LPF and (b) a HPF. (i) Block diagram of the s...
Figure 5: Performances of the (a) M-PLL with the LPF and (b) S-PLL with the HPF. (i) Block diagrams of the me...
Figure 6: (a) M-PLL and (b) S-PLL waveforms at (i) f0 = 150 kHz and (ii) f0 = 3 MHz.
Figure 7: Performances of the (a) M-PLL with the LPF and (b) S-PLL with the HPF. (i) Block diagrams of the se...
Figure 8: Frequency power spectral density (PSD) distributions of the output signals from the (a, b) M-PLL an...
Figure 9: (a) High-speed FM-AFM images of calcite (10−14) surface obtained in water at 0.5 s/frame (10 × 5 nm2...